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integrated circuit systems, inc. general description features ICS9148-93 advance information block diagram pentium is a trademark of intel corporation i 2 c is a trademark of philips corporation frequency generator & integrated buffers for pentium/pro tm 9148-93 rev - 1/22/99 pin configuration ? generates the following system clocks: - 4 cpu(2.5v/3.3v) upto 100mhz. - 6 pci(3.3v) @ 33.3mhz - 2agp(3.3v) @ 2 x pci - 12 sdrams(3.3v) @ either cpu or agp - 2 ref (3.3v) @ 14.318mhz ? skew characteristics: - cpu ? cpu <250ps - sdram ? sdram < 250ps - cpu ? sdram < 250ps - cpu(early) ? pci : 1-4ns ? supports spread spectrum modulation +0.25, 0.6% ? serial i 2 c interface for power management, frequency select, spread spectrum. ? efficient power management scheme through pci and cpu stop clocks. ? uses external 14.318mhz crystal ? 48 pin 300mil ssop. 48-pin ssop power groups vdd1 = ref (0:1), x1, x2 vdd2 = pciclk_f, pciclk(0:5) vdd3 = sdram (0:11), supply for pll core, 24 mhz, 48mhz vdd4 = agp (0:1) vddl = cpuclk (0:3) * internal pull-up resistor of 240k to 3.3v on indicated inputs the ICS9148-93 is the single chip clock solution for desktop/ notebook designs using the via mvp3 style chipset. it provides all necessary clock signals for such a system. spread spectrum may be enabled through i 2 c programming. spread spectrum typically reduces system emi by 8db to 10db. this simplifies emi qualification without resorting to board design iterations or costly shielding. the ICS9148-93 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. serial programming i 2 c interface allows changing functions, stop clock programming and frequency selection. the sd_sel latched input allows the sdram frequency to follow the cpuclk frequency(sd_sel=1) or the agp clock frequency(sd_sel=0). advance information documents contain information on products in the formative or design phase development. characteristic data and other specifications are design goals. ics reserves the right to change or discontinue these products without notice.
2 ICS9148-93 advance information pin descriptions notes: 1: internal pull-up resistor of 240k to 3.3v on indicated inputs 2: bidirectional input/output pins, input logic levels are latched at internal power-on-reset. use 10kohm resistor to program logic hi to vdd or gnd for logic low. r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 11 d d vr w pv 3 . 3 l a n i m o n , y l p p u s r e w o p l a t x , ) 2 : 0 ( f e r 2 0 f e rt u o. k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 5 . 2 _ # 3 . 3 u p c 2 , 1 n i v 3 . 3 = w o l , u p c v 5 . 2 = h g i h . v 5 . 2 r o v 3 . 3 s i 2 l d d v r e h t e h w s e t a c i d n i u p c 1 t u p n i d e h c t a l . 2 , 7 2 , 2 2 , 6 1 , 9 , 3 5 4 , 9 3 , 3 3 d n gr w pd n u o r g 41 xn i k c a b d e e f d n a ) f p 3 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c 2 x m o r f r o t s i s e r 52 xt u o d a o l l a n r e t n i s a h . z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c ) f p 3 3 ( p a c 4 1 , 62 d d vr w pv 3 . 3 l a n i m o n , ) 5 : 0 ( k l c i c p d n a f _ k l c i c p r o f y l p p u s 7 f _ k l c i c pt u o w e k s s n 4 - 1 h t i w s k l c u p c h t i w s u o n o r h c n y s . t u p t u o k c o l c i c p g n i n n u r e e r f # p o t s _ i c p y b d e t c e f f a t o n s i s i h t ) y l r a e u p c ( 1 s f 2 , 1 n i e h t s e n i m r e t e d s n i p s f r e h t o h t i w g n o l a . t u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f . s e i c n e u q e r f p g a & i c p , m a r d s , u p c 8 0 k l c i c pt u o ) y l r a e u p c ( w e k s s n 4 - 1 h t i w s k l c u p c s u o n o r h c n y s . t u p t u o k c o l c i c p 2 s f 2 , 1 n i e h t s e n i m r e t e d s n i p s f r e h t o h t i w g n o l a t u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f . s e i c n e u q e r f p g a & i c p , m a r d s , u p c 3 1 , 2 1 , 1 1 , 0 1) 4 : 1 ( k l c i c pt u o ) y l r a e u p c ( w e k s s n 4 - 1 h t i w s k l c u p c s u o n o r h c n y s . s t u p t u o k c o l c i c p 7 4 , 5 1) 1 : 0 ( p g at u o. 4 d d v y b d e r e w o p , s t u p t u o t r o p c i h p a r g d e c n a v d a 7 1 # p o t s _ u p c 1 n i 0 c i g o l t a s k c o l c ) 1 : 0 ( p g a d n a ) 3 : 0 ( k l c u p c s t l a h t u p n i s u o n o r h c n y s a s i h t ) 0 = e d o m , e d o m e l i b o m n i ( w o l t u p n i n e h w , l e v e l 1 1 m a r d st u o . t u p n i d e h c t a l l e s _ d s e h t y b d e t c e l e s s i y c n e u q e r f . t u p t u o k c o l c m a r d s y c n e u q e r f u p c = y c n e u q e r f m a r d s s e s u a c n o r e w o p t a 1 = l e s _ d s y c n e u q e r f p g a = y c n e u q e r f m a r d s s e s u a c n o r e w o p t a 0 = l e s _ d s 8 1 # p o t s _ i c p 1 n i n e h w , l e v e l 0 c i g o l t a s k c o l c ) 5 : 0 ( k l c i c p s t l a h t u p n i s u o n o r h c n y s a s i h t ) 0 = e d o m , e d o m e l i b o m n i ( w o l t u p n i 0 1 m a r d st u o . t u p n i d e h c t a l l e s _ d s e h t y b d e t c e l e s s i y c n e u q e r f . t u p t u o k c o l c m a r d s y c n e u q n e r f u p c = y c n e u q e r f m a r d s s e s u a c n o r e w o p t a 1 = l e s _ d s y c n e u q e r f p g a = y c n e u q e r f m a r d s s e s u a c n o r e w o p t a 0 = l e s _ d s , 1 3 , 9 2 , 8 2 , 1 2 , 0 2 8 3 , 7 3 , 5 3 , 4 3 , 2 3 ) 9 : 0 ( m a r d st u o . t u p n i d e h c t a l l e s _ d s e h t y b d e t c e l e s s i y c n e u q e r f . s t u p t u o k c o l c m a r d s y c n e u q e r f u p c = y c n e u q e r f m a r d s s e s u a c n o r e w o p t a 1 = l e s _ d s y c n e u q e r f p g a = s e i c n e u q e r f m a r d s s e s u a c n o r e w o p t a 0 = l e s _ d s 6 3 , 0 3 , 9 13 d d vr w p , s k c o l c z h m 8 4 , 4 2 d n a e r o c u p c , ) 1 1 : 0 ( m a r d s r o f y l p p u s . v 3 . 3 l a n i m o n 3 2a t a d sn ii r o f t u p n i a t a d 2 . t u p n i l a i r e s c 4 2k l c sn ii f o t u p n i k c o l c 2 t u p n i c 5 2 z h m 4 2t u o. g n i m i t o / i r e p u s r o f , k c o l c t u p t u o z h m 4 2 e d o m 2 , 1 n i . e d o m e l i b o m = 0 , e d o m p o t k s e d = 1 , n i p t c e l e s n o i t c n u f 8 1 n i p , 7 1 n i p . t u p n i d e h c t a l 6 2 z h m 8 4t u o. g n i m i t b s u r o f , k c o l c t u p t u o z h m 8 4 0 s f 2 , 1 n i e h t s e n i m r e t e d s n i p s f r e h t o h t i w g n o l a t u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f . s e i c n e u q e r f p g a & i c p , m a r d s , u p c 4 4 , 3 4 , 1 4 , 0 4) 3 : 0 ( k l c u p ct u ow o l = # p o t s _ u p c f i w o l . 2 l d d v y b d e r e w o p , s t u p t u o k c o l c u p c 2 4l d d vr w pl a n i m o n v 3 . 3 r o v 5 . 2 r e h t i e , ) 3 : 0 ( u p c r o f y l p p u s 6 4 1 f e rt u o. k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 l e s _ d sn i p g a r o ) 1 = l e s d s ( u p c r e h t i e s t c e l e s n o r e w o p t a t u p n i d e h c t a l . s t u p t u o k c o l c m a r d s e h t r o f s e i c n e u q e r f ) 0 = l e s _ d s ( 8 44 d d vr w p) 1 : 0 ( p g a r o f y l p p u s
3 ICS9148-93 advance information functionality v dd 1, 2, 3, 4 = 3.3v5%, v ddl = 2.5v 5% or 3.3 5%, ta= 0 to 70c crystal (x1, x2) = 14.31818mhz 5 . 2 _ # 3 . 3 u p c l e v e l t u p n i ) a t a d d e h c t a l ( r o f d e t c e l e s r e f f u b : t a n o i t a r e p o 1d d v v 5 . 2 0d d v v 3 . 3 cpu 3.3#_2.5v buffer selector for cpuclk drivers. power management functionality mode pin - power management input control 5 2 n i p , e d o m ) t u p n i d e h c t a l ( 7 1 n i p8 1 n i p 0 # p o t s _ u p c ) t u p n i ( # p o t s _ i c p ) t u p n i ( 1 1 1 m a r d s ) t u p t u o ( 0 1 m a r d s ) t u p t u o ( # p o t s _ u p c# p o t s _ i c p , p g a k l c u p c s t u p t u o k l c i c p ) 5 : 0 ( , f _ k l c i c p , f e r z h m 8 4 / 4 2 m a r d s d n a l a t s y r c c s o o c v 01 w o l d e p p o t sg n i n n u rg n i n n u rg n i n n u rg n i n n u r 11 g n i n n u rg n i n n u rg n i n n u rg n i n n u rg n i n n u r 10 g n i n n u rw o l d e p p o t sg n i n n u rg n i n n u rg n i n n u r 2 s f1 s f0 s f ) z h m ( u p c ) z h m ( m a r d s ) z h m ( i c p) z h m ( p g a 000 0 0 . 0 90 0 . 0 30 0 . 0 6 001 2 8 . 6 61 4 . 3 32 8 . 6 6 010 9 4 . 8 65 2 . 4 39 4 . 8 6 011 0 0 . 5 75 . 7 30 0 . 5 7 100 0 0 . 5 70 0 . 0 30 0 . 0 6 10 1 1 3 . 3 82 3 . 3 34 6 . 6 6 110 5 2 . 5 95 7 . 1 30 5 . 3 6 111 0 0 . 0 0 13 3 . 3 36 6 . 6 6
4 ICS9148-93 advance information byte0: functionality and frequency select register (default = 0) serial configuration command bitmap general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: ? send the address d2 (h) . ? send two additional dummy bytes, a command code and byte count. ? send the desired number of data bytes. see the diagram below: note that the acknowledge bit is sent by the clock chip, and pulls the data line low. there is no minimum of data bytes that mu st be sent. how to read: ? send the address d3 (h) . ? send the byte count in binary coded decimal ? read back the desired number of data bytes see the diagram below: the following specifications should be observed: 1. operating voltage for i 2 c pins is 3.3v 2. maximum data transfer rate (sclk) is 100k bits/sec. r o t a r e n e g k c o l c ) s t i b 7 ( s s e r d d a k c a s t i b 8 + y m m u d e d o c d n a m m o c k c a s t i b 8 + e t y b y m m u d t n u o c k c a e t y b a t a d 1 k c a e t y b a t a d n k c a # w / r & ) 0 : 6 ( a 2 d) h ( r o t a r e n e g k c o l c ) s t i b 7 ( s s e r d d a k c a e t y b t n u o c k c a e t y b a t a d 1 k c a e t y b a t a d n # w / r & ) 0 : 6 ( a 3 d) h ( i 2 c is a trademark of philips corporation note 1. default at power-up will be for latched logic inputs, as defined by bit 3. t i bn o i t p i r c s e dd w p 7 t i b n o i t a l u d o m m u r t c e p s d a e r p s % 5 2 . 0 - 0 n o i t a l u d o m m u r t c e p s d a e r p s % 6 . 0 - 1 0 t i b 4 : 6 ) 4 : 6 ( t i bu p c m a r d s ) z h m ( i c p ) z h m ( p g a ) z h m ( x x x 1 e t o n 0 0 00 0 . 0 90 0 . 0 30 0 . 0 6 1 0 02 8 . 6 61 4 . 3 32 8 . 6 6 0 1 09 4 . 8 65 2 . 4 39 4 . 8 6 1 1 00 0 . 5 70 5 . 7 30 0 . 5 7 0 0 10 0 . 5 70 0 . 0 30 0 . 0 6 1 0 11 3 . 3 82 3 . 3 34 6 . 6 6 0 1 15 2 . 5 95 7 . 1 30 5 . 3 6 1 1 10 0 . 0 0 13 3 . 3 36 6 . 6 6 3 t i b , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r f - 0 y l n o s n i p ) 2 : 0 ( s f i y b s e i c n e u q e r f t c e l e s - 1 2 c 0 d a e r p s r e t n e c - 0 d a e r p s n w o d - 1 0 1 t i b n o i t a r e p o l a m r o n - 0 d e l b a n e m u r t c e p s d a e r p s - 1 0 0 t i b g n i n n u r - 0 s t u p t u o l l a e t a t s i r t - 1 0
5 ICS9148-93 advance information byte 1: cpu, active/inactive register (1 = enable, 0 = disable) byte 2: pci active/inactive register (1 = enable, 0 = disable) byte 3: sdram active/inactive register (1 = enable, 0 = disable) notes: 1. inactive means outputs are held low and are disabled from switching. notes: 1. inactive means outputs are held low and are disabled from switching. notes: 1. inactive means outputs are held low and are disabled from switching. t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b-1 ) d e v r e s e r ( 3 t i b0 41 ) t c a n i / t c a ( 3 k l c u p c 2 t i b1 41 ) t c a n i / t c a ( 2 k l c u p c 1 t i b3 41 ) t c a n i / t c a ( 1 k l c u p c 0 t i b4 41 ) t c a n i / t c a ( 0 k l c u p c t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b71 ) t c a n i / t c a ( f _ k l c i c p 5 t i b5 11 ) t c a n i / t c a ( 0 p g a 4 t i b3 11 ) t c a n i / t c a ( 4 k l c i c p 3 t i b2 11 ) t c a n i / t c a ( 3 k l c i c p 2 t i b1 11 ) t c a n i / t c a ( 2 k l c i c p 1 t i b0 11 ) t c a n i / t c a ( 1 k l c i c p 0 t i b81 ) t c a n i / t c a ( 0 k l c i c p t i b# n i pd w pn o i t p i r c s e d 7 t i b8 21 ) t c a n i / t c a ( 7 m a r d s 6 t i b9 21 ) t c a n i / t c a ( 6 m a r d s 5 t i b1 31 ) t c a n i / t c a ( 5 m a r d s 4 t i b2 31 ) t c a n i / t c a ( 4 m a r d s 3 t i b4 31 ) t c a n i / t c a ( 3 m a r d s 2 t i b5 31 ) t c a n i / t c a ( 2 m a r d s 1 t i b7 31 ) t c a n i / t c a ( 1 m a r d s 0 t i b8 31 ) t c a n i / t c a ( 0 m a r d s byte 4: sdram active/inactive register (1 = enable, 0 = disable) byte 5: peripheral active/inactive register (1 = enable, 0 = disable) notes: 1. inactive means outputs are held low and are disabled from switching. notes: 1. inactive means outputs are held low and are disabled from switching. t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b-1 ) d e v r e s e r ( 3 t i b7 11 ) t c a n i / t c a ( 1 1 m a r d s ) y l n o e d o m p o t k s e d ( 2 t i b8 11 ) t c a n i / t c a ( 0 1 m a r d s ) y l n o e d o m p o t k s e d ( 1 t i b0 21 ) t c a n i / t c a ( 9 m a r d s 0 t i b1 21 ) t c a n i / t c a ( 8 m a r d s t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b7 41 ) t c a n i / t c a ( 1 p g a 3 t i b-1 ) d e v r e s e r ( 2 t i b-1 ) d e v r e s e r ( 1 t i b6 41 ) t c a n i / t c a ( 1 f e r 0 t i b21 ) t c a n i / t c a ( 0 f e r
6 ICS9148-93 advance information cpu_stop# timing diagram cpu_stop# is an asychronous input to the clock synthesizer. it is used to turn off the cpu clocks for low power operation. cpu_stop# is synchronized by the ICS9148-93 . the minimum that the cpu clock is enabled (cpu_stop# high pulse) is 100 cpu clocks. all other clocks will continue to run while the cpu clocks are disabled. the cpu clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. cpu clock on latency is less than 4 cpu clocks and cpu clock off latency is less than 4 cpu clocks. notes: 1. all timing is referenced to the internal cpu clock. 2. cpu_stop# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpu clocks inside the ICS9148-93. 3. all other clocks continue to run undisturbed. (including sdram outputs).
7 ICS9148-93 advance information pci_stop# timing diagram pci_stop# is an asynchronous input to the ICS9148-93 . it is used to turn off the pciclk (0:5) clocks for low power operation. pci_stop# is synchronized by the ICS9148-93 internally. the minimum that the pciclk (0:5) clocks are enabled (pci_stop# high pulse) is at least 10 pciclk (0:5) clocks. pciclk (0:5) clocks are stopped in a low state and started with a full high pul se width guaranteed. pciclk (0:5) clock on latency cycles are only one rising pciclk clock off latency is one pciclk clock. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9148 device.) 2. pci_stop# is an asynchronous input, and metastable conditions may exist. this signal is required to be synchronized inside the ics9148. 3. all other clocks continue to run undisturbed. 4. cpu_stop# is shown in a high (true) state.
8 ICS9148-93 advance information pins 2, 7, 8, 25, 26 and 46 on the ICS9148-93 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm(10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. figs. 1 and 2 show the recommended means of implementing this function. in fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the device?s internal logic. figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. shared pin operation - input/output pins fig. 1 these figures illustrate the optimal pcb physical layout options. these configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. the layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s).
9 ICS9148-93 advance information fig. 2a fig. 2b
10 ICS9148-93 advance information absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c case temperature . . . . . . . . . . . . . . . . . . . . . . . . 115c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = v ddl = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 0.15ma input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 2.0 ma input low current i il2 v in = 0 v; inputs with pull-up resistors -200 -100 ma operating i dd3.3op c l = 0 pf; 66.8 mhz 100 160 ma supply current input frequency f i v dd = 3.3 v; 14.318 mhz input capacitance 1 c in logic inputs 5 pf c inx x1 & x2 pins 27 36 45 pf transition time 1 t trans to 1st crossing of target freq. 2 ms settling time 1 t s from 1st crossing to 1% target freq. ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 2 ms skew 1 t cpu-sdram1 v t = 1.5 v; sdram leads -500 200 500 ps t cpu-pci1 v t = 1.5 v; cpu leads 12.84 ns 1 guaranteed by design, not 100% tested in production. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units operating i dd2.5op c l = 0 pf; 66.8 mhz 10 20 ma supply current t cpu-sdram2 v t = 1.5 v; v tl = 1.25 v; sdram leads -500 200 500 ps t cpu-pci2 v t = 1.5 v; v tl = 1.25 v; cpu leads 12.74 ns 1 guaranteed by design, not 100% tested in production. skew 1
11 ICS9148-93 advance information electrical characteristics - cpu t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh2 a i oh = -28 ma 2.5 2.6 v output low voltage v ol2a i ol = 27 ma 0.35 0.4 v output high current i oh2 a v oh = 2.0 v -29 -23 ma output low current i ol2 a v ol = 0.8 v 33 37 ma rise time t r2a 1 v ol = 0.4 v, v oh = 2.4 v 1.75 2 ns fall time t f2a 1 v oh = 2.4 v, v ol = 0.4 v 1.1 2 ns duty cycle d t2a 1 v t = 1.5 v 45 50 55 % skew t sk2a 1 v t = 1.5 v 50 250 ps jitter, one sigma t j1s2a 1 v t = 1.5 v 65 150 ps jitter, absolute t jabs2a 1 v t = 1.5 v -250 165 250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - cpu t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol c onditions min typ max units output high voltage voh2b i oh = -8 ma 2 2.2 v output low voltage vol2b i ol = 12 ma 0.3 0.4 v output high current ioh2b v oh = 1.7 v -20 -16 ma output low current iol2b v ol = 0.7 v 19 26 ma rise time tr2b 1 v ol = 0.4 v, v oh = 2.0 v 1.5 1.8 ns fall time tf2b 1 v oh = 2.0 v, v ol = 0.4 v 1.6 1.8 ns duty cycle dt2b 1 v t = 1.25 v 404755% skew tsk2b 1 v t = 1.25 v 60 250 ps jitter, single edge displacement 2 tjsed2b 1 v t = 1.25 v 200 250 ps jitter, one sigma tj1s2b 1 v t = 1.25 v 65 150 ps jitter, absolute tjabs2b 1 v t = 1.25 v -300 160 300 ps 1 guaranteed by design, not 100% tested in production. 2 edge displacement of a period relative to a 10-clock-cycle rolling average period.
12 ICS9148-93 advance information electrical characteristics - pci t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh1 i oh = -28 ma 2.4 3 v output low voltage v ol1 i ol = 23 ma 0.2 0.4 v output high current i oh1 v oh = 2.0 v -60 -40 ma output low current i ol1 v ol = 0.8 v 41 50 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 1.8 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 1.6 2 ns duty cycle d t1 1 v t = 1.5 v 45 51 55 % skew t sk1 1 v t = 1.5 v 130 250 ps jitter, one sigma 1 t j1s1a v t = 1.5 v, synchronous 40 150 ps t j1s1b v t = 1.5 v, asynchronous 200 250 ps jitter, absolute 1 tab s1a v t = 1.5 v, synchronous -250 135 250 ps t jabs1b v t = 1.5 v, asynchronous -650 500 650 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - sdram t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 30 pf parameter symbol conditions min typ max units output high voltage v oh1 i oh = -28 ma 2.4 3 v output low voltage v ol1 i ol = 23 ma 0.2 0.4 v output high current i oh1 v oh = 2.0 v -60 -40 ma output low current i ol1 v ol = 0.8 v 41 50 ma rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 1.75 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 1.5 2 ns duty cycle 1 d t1 v t = 1.5 v 45 50 55 % skew 1 t sk1 v t = 1.5 v 200 500 ps jitter, one sigma 1 t j1s1 v t = 1.5 v 50 150 ps jitter, absolute 1 t jabs1 v t = 1.5 v (with synchronous pci) -250 +250 ps jitter, absolute 1 t jabs1 v t = 1.5 v (with asynchronous pci) -400 400 ps 1 guaranteed by design, not 100% tested in production.
13 ICS9148-93 advance information electrical characteristics - agp t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh1 i oh = -28 ma 2.4 3 v output low voltage v ol1 i ol = 23 ma 0.2 0.4 v output high current i oh1 v oh = 2.0 v -60 -40 ma output low current i ol1 v ol = 0.8 v 41 50 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 1.1 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 1 2 ns duty cycle d t1 1 v t = 1.4 v 45 49 55 % skew t sk1 1 v t = 1.5 v 130 250 ps jitter, one sigma 1 t j 1s1 v t = 1.5 v 2 3 % jitter, absolute 1 t abs1a v t = 1.5 v, synchronous -5 2.5 5 % t jabs1b v t = 1.5 v, asynchronous -6 4.5 6 % 1 guaranteed by design, not 100% tested in production. electrical characteristics - 24mhz, 48mhz, ref0 t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 10 -20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -16 ma 2.4 2.6 v output low voltage v ol5 i ol = 9 ma 0.3 0.4 v output high current i oh5 v oh = 2.0 v -32 -22 ma output low current i ol5 v ol = 0.8 v 16 25 ma rise time t r5 1 v ol = 0.4 v, v oh = 2.4 v 2 4 ns fall time t f5 1 v oh = 2.4 v, v ol = 0.4 v 1.9 4 ns duty cycle d t5 1 v t = 1.5 v 45 54 57 % jitter, one sigma t j1s5 1 v t = 1.5 v 1 3 % jitter, absolute t jabs5 1 v t = 1.5 v -5 - 5 % 1 guaranteed by design, not 100% tested in production.
14 ICS9148-93 advance information ssop package ordering information ics9148f-37 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx f - ppp l o b m y s s n o i s n e m i d n o m m o c s n o i t a i r a v d n . n i m. m o n. x a m. n i m. m o n. x a m a5 9 0 .1 0 1 .0 1 1 .c a0 2 6 .5 2 6 .0 3 6 .8 4 1 a8 0 0 .2 1 0 .6 1 0 . 2 a8 8 0 .0 9 0 .2 9 0 . b8 0 0 .0 1 0 .5 3 1 0 . c5 0 0 .- 0 1 0 . ds n o i t a i r a v e e s e2 9 2 .6 9 2 .9 9 2 . ec s b 5 2 0 . 0 h0 0 4 .6 0 4 .0 1 4 . h0 1 0 .3 1 0 .6 1 0 . l4 2 0 .2 3 0 .0 4 0 . ns n o i t a i r a v e e s 0 5 8 x5 8 0 .3 9 0 .0 0 1 . advance information documents contain information on products in the formative or design phase development. characteristic data and other specifications are design goals. ics reserves the right to change or discontinue these products without notice.

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